The present invention relates to a semiconductor integrated circuit device and, more particularly, to a semiconductor memory device which is suitable for high speed and low power consumption operations and to a semiconductor data processor such as a microcomputer or a microprocessor using such a semiconductor memory device.
Employing techniques for lower power consumption is essential for elongating the lifetime of a battery in a PDA (Personal Digital Assistant) or a portable personal computer. In a high end microcomputer, too, the problem of heat generation resulting from power consumption becomes serious in the sense of deteriorating the reliability of the device.
A known technique for reducing the power consumption of a memory circuit is exemplified in the prior art by lowering the supply voltage, as disclosed on pp. 53 and 54 of 1990 Symposium on VLSI Circuit, Digest of Technical Papers (1990), which is hereinafter referred to as prior art(1).
There is another method by which a memory of smaller capacity is placed in a lower hierarchy of an architecture having a multi-hierarchy memory, as disclosed on pp. 16 and 17 of 1994 IEEE Symposium on Low Lower Electronics, Digest of Technical Papers (1994) (Prior Art 2). Generally speaking, a memory of the smaller storage capacity can be constructed to have the lower load resistance and capacity in its bit lines or the like so that it can be operated in the lower power consumption. In this example of the prior art, the power consumption is reduced by enhancing the frequency of accessing the memory of as low hierarchy as possible to have the smaller capacity, i.e., the memory of the lower power consumption.
A portable information device of high-speed and low power consumption is realized with a cache memory built-into a semiconductor data processor, such as a microprocessor, providing a high hit ratio. Since the access of an off chip memory, of which a load is large, can be decreased with a built-in type of cache memory providing a high hit ratio, the power consumption of the whole portable information device can be reduced. And, because the access of the memory of which the latency is long decreases, speed-up can be attained.
Recent trends have resulted in the storage capacity of the memory installed in a semiconductor data processor such as a microcomputer or a microprocessor to be increased. As a result, the number of memory cells connected to the bit lines of the memory array of the internal memory has increased (which enlarges the load) to increase the access time. In order to shorten this access time, therefore, it is necessary to increase the current of the memory cells. This increase in the current of the memory cells can be realized by lowering the threshold voltage of the MOS (Metal-Oxide-Semiconductor) transistors. However, the present inventors have found that the lowering of the threshold voltage brings about the following problem in a low supply voltage range of 1 V.
FIG. 14 illustrates the static noise allowance of the memory cells for the threshold voltages (Vth) of 0.5 V and 0.3 V when the supply voltage is 1 V. As illustrated in FIG. 14, the static noise allowance is 0.4 V for vth=0.5 V and is 0.25 V for Vth=0.3 V. In other words, the static noise allowance is reduced by 38% if the threshold voltage is lowered by 0.2 V. From the standpoint of reliability, therefore, there arises a problem that the threshold voltage of a MOS transistor composing memory cells cannot be lowered.
If, moreover, a memory of large storage capacity is used in the low voltage operation, the following problem arises, as found by the inventors.
FIG. 15 illustrates the dependency of the read rate on the supply voltage in a secondary cache memory (L2-cache) of 16 Kbytes and a primary cache memory (L1-cache) of 2 Kbytes. The pie charts show the ratios (which means the memory cell current ability) of the time period till a predetermined potential difference arises in the bit line pairs (that is, the time period till the sense amplifier can be started, which will be hereinafter referred to as the memory cell time) to the entire read time period. In the supply voltage range as high as 2.5 V or the like, as shown in FIG. 15, the portion, which is occupied by the memory cell time period of the primary cache memory and the secondary cache memory, is as low as 30% or less. In the supply voltage range as low as 1 V or the like, however, the portion, which is occupied by the memory cell time period of the secondary cache memory, exceeds 50%, as shown in FIG. 15. In short, in order to improve the read time period in the supply voltage range as low as 1 V or the like, it is necessary to increase the current of the memory cells. As described above, however, the threshold voltage of a MOS transistor composing memory cells cannot be lowered.
In the prior art (1), the memory which is operable at the supply voltage of 1 V is described, but there is no description of the aforementioned problem which has been found out by the inventors.
As described in connection with the prior art (2), moreover, the method of arranging a plurality of memories of small storage capacity requires the use of a peripheral circuit such as a decoder for each memory, which brings about the problem enlarging the circuit scale. On the other hand, when the power consumed by the memory array itself can be reduced, there arises a problem that the power consumed by the peripheral circuit or the like, due to the arrangement of the plurality of memories, increases.
For the known techniques, therefore, it is difficult to solve all of the considerations involving attempts at reducing power consumption, to speed up the operations and to reduce the circuit scale.
An object of the present invention is to provide a semiconductor memory device capable of operating at high speed and with low power consumption, and a semiconductor data processing device having such a semiconductor memory device packaged therein.
Another object of the present invention is to provide a memory structure/circuit capable of solving the aforementioned problem of the reduction of speed due to the low voltage.
Yet another object of the present invention is to provide a memory structure/circuit capable of solving the problem of the increase in the circuit scale when memory arrays are connected together in a hierarchy.
A further object of the present invention is to provide a cache memory which is suited to be packaged in a data processing device such as a microprocessor.
A representative one of the inventions disclosed herein will be briefly summarized in the following.
(1) A semiconductor memory device has: a first memory array (MAS) including a plurality of word lines (WS1 and so on), a first bit line pair (BS1, BSB1 and so on), and a plurality of memory cells (M) arranged at the intersections of the plurality of word lines and the first bit line pair; a second memory array (MAF) including a plurality of word lines (WF1 and so on), a second bit line pair (BF1, BFB1 and so on), and a plurality of memory cells (M) arranged at the intersections of the plurality of word lines and the second bit line pair; a sense amplifier (SA1 and so on) for amplifying a signal outputted to the second bit line pair; and switch means (HS1) for controlling the connection between the first bit line pair and the second bit line pair, wherein a signal outputted to the first bit line pair is transmitted through the switch means and the second bit line pair to the sense amplifier.
(2) A semiconductor memory device has: a first memory array (MAS) including a plurality of word lines (WS1-WSp), a first bit line pair (M) arranged at the intersections of the plurality of word lines and the first bit line pair; and a second memory array (MAE) including a plurality of word lines (WF1-WFq), a second bit line pair (BF1, BFB1-BFn, BFBn), and a plurality of memory cells (M) arranged at the intersections of the plurality of word lines and the second bit line pair, wherein the number of word lines included in the second memory array is smaller than that of word lines included in the first memory array, and wherein the first bit line pair and the second bit line pair are connected through switch means whose electrical connection state is controlled by a control signal (HS1).
(3) A semiconductor memory device has: first and second word line groups including a plurality of word lines; first and second bit line pair groups including a plurality of bit line pairs; and a plurality of memory cells (M) arranged in a matrix form at the intersections between the first word line group and the first bit line group and at the intersections between the second word line group and the second bit line group, wherein each bit line pair (BS1, BSB1-BSn, BSBn) of the first bit line pair group and each bit line pair (BF1, BFB1-BFn, BFBn) of the second bit line pair group are connected through first switch means (HS1 and so on),
(4) A semiconductor memory device has first, second and third memory cell arrays (DAS, DAF and TAF) and a comparator (CMP1), wherein each of the first, second and third memory cell arrays includes a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells arranged at the intersections between the plurality of word lines and the plurality of bit line pairs, wherein each bit line pair of the first memory cell array and each bit line pair of the second memory cell array are connected through switch means, wherein the comparator compares the address signal with the stored content of the third memory cell array, and wherein the switch means is turned on if the comparator indicates a difference in the result of the comparison.
(5) A semiconductor memory device has first, second and third memory cell arrays (MAS, MAF and MAT), wherein each of the first, second and third memory cell arrays includes a plurality of word lines (WS1-WSp, WF1-WFq, WT1-WTu), a plurality of bit lines (BS1, BSB1; BF1, BFB1; BT1, BFB1 and so on), and a plurality of memory cells (M) arranged at the intersections between the plurality of word lines and the plurality of bit lines, wherein the bit lines of the first memory cell array and the bit lines of the second memory cell arrays are individually connected through first switch means (HS1, HSB1 and so on), and wherein the bit lines of the first memory cell array and the bit lines of the third memory cell array are individually connected through second switch means (HT1, HTB1 and so on).
(6) A semiconductor memory device has: a first memory array (MAS) including a plurality of first word lines (WS1-WSp), a first bit line pair (BS1, BSB1 and so on), and a plurality of memory cells (M) arranged at the intersections of the plurality of word lines and the first bit line pair; a second memory array (MAF) including a plurality of second word lines (WF1-WFq), second and third bit line pairs (BF1, BFB1; BF1T, BFB1T and so on), and a plurality of dual port memory cells (D) arranged at the intersections of the plurality of word lines and the second and third bit line pairs and connected to the second and third bit line pairs; first switch means (HS1 and so on) connected between the first bit line pair and the second bit line pair; second switch means (HU1 and so on) connected between the first bit line pair and the third bit line pair, a first sense amplifier circuit (SA1 and so on) for amplifying the output of the second bit line pair; and a second sense amplifier circuit (SA1U and so on) for amplifying the output of the third bit line pair.
(7) A semiconductor memory device has: a first memory array (MAS) including a plurality of first word lines (WS1 and so on), a first bit line pair (SS1, SSB1 and so on), and a plurality of memory cells (M) arranged at the intersections of the plurality of word lines and the first bit line pair, a second memory array (MAF) including a plurality of second word lines (WF1 and so on), a second bit line pair SF1, SFB1 and so on), and a plurality of memory cells (M) arranged at the intersections of the plurality of word lines and the second bit line pair; and a third bit line pair (BF1, BFB1, and so on) connected to the first bit line pair through first switch means (HF1 and so on) and connected to the second bit line pair through second switch means (HE1 and so on), wherein the length of the second bit line pair is smaller than that of the first bit line pair.
(8) A semiconductor device has first, second, third and fourth memory cell arrays and a comparator, wherein each of the first, second, third and fourth memory cell arrays includes a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells arranged at the intersections between the plurality of word lines and the plurality of bit line pairs, wherein the individual bit line pairs of the first memory cell array and the individual bit line pairs of the second memory cell array are connected through first switch means, wherein the individual bit line pairs of the third memory cell array and the individual bit line pairs of the fourth memory cell array are connected through second switch means, and wherein the address signal is compared with the stored content of the second memory cell array by the comparator, and if the result of comparison of the comparator is inconsistency, the first and second switch means are turned on.
(9) A semiconductor data processor has: a CPU and a memory device connected to the CPU through a bus, both the CPU and the memory device being formed on a single semiconductor substrate, wherein the memory device includes: a first tag array for storing a plurality of address data at the same address; a first data array for storing a plurality of data at the same address; a second tag array for storing a plurality of address data at the same address; a second data array for storing a plurality of data at the same address; and a plurality of comparators for comparing an address signal inputted from the bus and the address data stored in the first or second tag array, wherein the bit lines of the first tag array and the bit lines of the second tag array are connected through first switch means, wherein the bit lines of the first data array and the bit lines of the second data array are connected through second switch means, wherein sense amplifiers are individually connected to the bit lines of the first tag array and the first data array, and wherein the outputs of the sense amplifiers connected to the bit lines of the first data array are connected with the bus.
(1) By turning on the switch means (HS1 and so on), the memory array can be used as one having a large storage capacity. By turning off the switch means (HS1 and so on), the bit lines of the first memory array (MAF) can be disconnected to lighten the load upon the bit lines of the second memory array (MAS). As a result, the memory cells of the second memory array (MAF) can be read out faster than those of the first memory array (MAS). The data read out frequently can be read out selectively fast if it is stored in the second memory array. Because of the light load on the bit lines, moreover, the power consumed by accessing the memory cells in the second memory array (MAF) can be made lower than that by accessing the memory cells in the first memory array (MAS). If data of high access frequency is stored in the second memory array, on the other hand, the effective power consumption designed by considering the access frequency can be efficiently reduced.
(2) If the number of word lines contained in the second memory array (MAF) is smaller than that of the word lines contained in the first memory array (MAS), the storage capacity of the second memory array (MAF) is reduced. If the data in the first memory array (MAS) is made to include the data. in the second memory array (MAF), the second memory array (MAF) can be used like a cache memory in the first memory array (MAS). If the data used frequently among the data of the first memory array (MAS) is stored in the second memory array (MAF), the speed can be effectively raised to reduce the power consumption.
(3) If the second memory array (DAF) is used as a data array of the primary cache memory, if the first memory array (DAS) is used as a data array or main memory of the secondary cache memory, if the third memory array (TAF) is used as a tag array of the primary cache memory and if the third memory array (TAF) has no desired address data, the data of the secondary cache memory or the main memory can be read out by turning on the switch means.
(4) By connecting the third memory array (MAT), the first memory array (MAS) and the second memory array (MAF) in this order by the second switch means (HT1 and so on) and the first switch means (HG1 and so on) and by turning off the first switch means (HS1 and so on) between the first memory array (MAS) and the second memory array (MAF), the reading of the second memory array (MAF) can be faster than the reading of the first memory array (MAS) and the third memory array (MAT). By turning off the second switch means (HT1 and so on) between the third memory array and the first memory array and by turning on the first switch means (HS1 and so on) between the first memory array (MAS) and the second memory array (MAF), the first memory array (MAS) can be read out faster than the third memory array (MAT). High speed reading can be realized if the data accessed frequently is stored in the second memory array (MAF) or the first memory array (MAS). The order of power consumption is the second memory array (MAF), the first memory array (MAS) and the third memory array (MAT), and the access to the second memory array (MAF) is the smallest.
(5) A dual port structure can be realized if the data in the first memory array (MAS) is given an inclusion relation between the data in the second memory array (MAF) and the data in the third memory array (MAT) and if a sense amplifier (SA1T) is connected to the third memory array (MAT). Thus, a dual port access can be effected at a high probability using memory cells M of single port. This can also be used as a cache memory, so that the dual port cache memory can be realized. Since the bit lines of the second memory array (MAF) can be provided separately from those of the first memory array (MAS) and since the bit lines of the third memory array (MAT) can be provided separately from those of the first memory array (MAS), the power consumption can be reduced, and the second memory array (MAF) and the third memory array (MAT) can be accessed at a high reading speed. Moreover, if the two ports of the dual port cache memory are connected to an instruction path and a data path, it is possible to realize a cache memory having both an instruction cache and a data cache, thereby to realize performance effectively similar to that of a separate cache by using a unified cache.
(6) The first memory array (MAS) and the second memory array (MAF) of the dual port memory are connected through the first switch means (HS1 and so on) and the second switch means (HU1 and so on). Since the second memory array (MAF) is made to have the dual ports, most memory accesses are made locally to the second memory array (MAF) having a dual port structure, so that the storage capacity of the second memory array (MAF) can be suppressed to restrict the area increase caused by the multi-port memory cells.
(7) The first memory array (MAS) and the second memory array (MAF) are individually connected to the common bit lines through the first switch means (HF1) and the second switch means (HE1), and the sense amplifier (SA1) is connected to the common bit lines on the second memory array side. As a result, if the second switch means is turned off, the load upon the bit lines of the second memory array disappears, so that the first memory array is read out fast.
(8) If the second memory array (TAF) and the first memory array (TAS) are used as a tag array and if the fourth memory array (DAF) and the third memory array (DAS) are used as the data array, the second memory array (TAF) and the fourth memory array (DAF) can be operated as cache memories of the first memory array (TAS) and the third memory array (DAS), to provide a cache memory which is equipped with the primary cache memory (TAF and DAF) and the secondary cache memory (TAS and DAS). The direct mapped type cache memory can be realized by using a set of tag arrays and data arrays, and the set-associative type cache memory can be realized if a plurality of sets of tag arrays and data arrays are used.
The foregoing and remaining objects and the novel features of the present invention will become apparent from the resent specification and the accompanying drawings.